RFSoC를 적용한 추적레이다용 신호처리부 부팅시간 단축을 위한 연구

김정은¹^{, *} ; 현효영² ; 이주호³ ; 김홍락²

1LIG 디펜스&에어로스페이스 선임연구원
2LIG 디펜스&에어로스페이스 수석연구원
3LIG 디펜스&에어로스페이스 연구원

A Study on Reducing the Boot Time of an RFSoC-Based Signal Processing Unit for Tracking Radar

JungEun Kim¹^{, *} ; Hyo Young Hyun² ; Ju-Ho Lee³ ; Hong-Rak Kim²

1Research engineer, LIG Defense&Aerospace
2Chief engineer, LIG Defense&Aerospace
3Research engineer, LIG Defense&Aerospace

Correspondence to: *JungEun Kim Missile System RF & IIR Seeker R&D Lab, LIG D&A, 207, Mabuk-ro, Giheung-gu, Yongin-si, Gyeonggi-do, Republic of Korea Tel: +82-31-525-0302 E-mail: jungeun.kim@ligdna.com

초록

본 논문에서는 RFSoC를 적용한 추적레이다용 신호처리기의 부팅 구조 설계 방안을 제안한다. 추적 레이다 시스템의 특성상 빠른 초기 기동이 요구되므로 효율적인 IC들의 부팅 설계가 필요하다. 따라서 기존 FPGA기반 신호처리기의 로직 구조를 유지한 상태에서 RFSoC를 적용하기 위하여 본 연구에서는 RFSoC의 부팅 절차를 분석한 후 Sub.FPGA를 추가하였다.

Abstract

In this paper, we propose a boot-structure design methodology for a tracking-radar signal processor implemented on an RFSoC. Because a tracking-radar system requires extremely rapid initial start-up, an efficient boot design for the constituent ICs is essential. Accordingly, while preserving the existing FPGA-based signal-processing logic, we first analyze the RFSoC boot procedure and then introduce an auxiliary sub-FPGA to enable the RFSoC-based implementation.

Keywords:

Tracking Radar, RFSoC Boot, DSP(Digital Signal Processing), Signal-Processing Unit, Boot Sequence

키워드:

추적레이다, RFSoC 부팅, 신호처리부, 부팅순서

References

Anil K. Maini, Handbook of Defence Electronics and Optronics: Fundamentals, Technologies and Systems, John Wiley & Sons, 2018. [https://doi.org/10.1002/9781119184737]
Jin-Kyu Choi, Chang-Hyun Park, Youn-Jin Kim, Hong-Rak Kim, Jun-Beom Kwon, & Gwang-Hee Kim, ‘A Design Study of Signal Processor for Small Tracking Radar,’ The Journal of the Institute of Internet, Broadcasting and Communication, VOL. 20, NO. 5, 2020, pp. 71-77.
Texas Instruments, TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor Datasheet, SPRS691E, 2010.
Gyuwon Lee, ‘RFSoC-Based Signal Processor Design for Compact Radar System,’ The Journal of the Institute of Internet, Broadcasting and Communication, VOL. 25, NO. 1, 2025, pp. 253-260.